Introduction to Logic Design

cd

1. HW3 SOLUTION (PDF)
2. LOGICLY FILE

Chapter 1 - Digital Systems and Binary Numbers

1.1  Digital Systems

1.2  Binary Numbers

1.3  Number-base Conversions

1.4  Octal and Hexadecimal Numbers

1.5  Complements

1.6  Signed Binary Numbers

1.7  Binary Codes

1.8  Binary Storage and Registers

1.9  Binary Logic

Chapter 1 presents the various binary systems suitable for representing information in digital systems. The binary number system is explained and binary codes are illustrated. Examples are given for addition and subtraction of signed binary numbers and decimal numbers in binary‐coded decimal (BCD) format.

M. Morris. Mano, “Digital Design”.

Chapter 2 introduces the basic postulates of Boolean algebra and shows the correlation between Boolean expressions and their corresponding logic diagrams. All possible logic operations for two variables are investigated, and the most useful logic gates used in the design of digital systems are identified. This chapter also introduces basic CMOS logic gates.

Additional reading material for laws and theorems of Boolean algebra. 

Summary of postulates.

3-1 The Map Method

Two-variable map and Three-variable map

3-2 Four-Variable Map

3-3 Five-variable Map

3-4 Product of Sums Simplification

3-5 Don’t-care Conditions

3-6 NAND and NOR Implementation

3-7 Other Two-Level Implementations

3-8 Exclusive-OR Function

SOLUTIONS OF MIDTERM EXAM QUESTIONS

Solution of Class Problem by using Quine Mc-Cluskey Method

This chapter covers the map method for simplifying Boolean expressions. The map method is also used to simplify digital circuits constructed with AND‐OR, NAND, or NOR gates. All other possible two‐level gate circuits are considered, and their method of implementation is explained. Verilog HDL is introduced together with simple examples of gate‐level models.

4.1  Introduction

This chapter outlines the formal procedures for the analysis and design of combinational circuits. Some basic components used in the design of digital systems, such as adders and code converters, are introduced as design examples. Frequently used digital logic functions such as parallel adders and subtractors, decoders, encoders, and multiplexers are explained, and their use in the design of combinational circuits is illustrated. HDL examples are given in gate‐level, dataflow, and behavioral models to show the alternative ways available for describing combinational circuits in Verilog HDL. The procedure for writing a simple test bench to provide stimulus to an HDL design is presented.

5.1       Introduction

5.2       Sequential Circuits

5.3       Storage Element: Latches

5.4       Storage Element: Flip-Flops

5.5       Analysis of Clocked Sequential Circuits

5.7       State Reduction and Assignment

5.8       Design Procedure

SOLUTIONS of FINAL EXAMINATION QUESTIONS

This chapter outlines the formal procedures for analysing and designing clocked (synchronous) sequential circuits. The gate structure of several types of flip‐flops is presented together with a discussion on the difference between level and edge triggering. Specific examples are used to show the derivation of the state table and state diagram when analysing a sequential circuit. A number of design examples are presented with emphasis on sequential circuits that use D‐type flip‐flops.

SOLUTIONS-FINAL EXAMINATION FALL 2016-17

MIDTERM EXAMINATION SOLUTIONS - Fall 2016-17