Topic outline
- General
- COURSE INSTRUCTORS
COURSE INSTRUCTORS
FALL 2017-18
LAB INSTRUCTORS
S. MOHAMMADZADEH
GULSHER L. BALOCH
MUSTAFA MULLA
MEHRAB K. ALLAHDAD
- COURSE DESCRIPTION
COURSE DESCRIPTION
EENG115/INFE115 Introduction to Logic Design
This is core course of Electrical and Elecronic Engineering and Information System Engineering that presents basic tools for the design of digital circuits. It serves as a building block in many disciplines that utilize data of digital nature like digital control, data communication, digital computers etc. The goal of this course is to;
1. perform arithmetic operations in many number systems.
2. manipulate Boolean algebraic structures.
3. simplify the Boolean expressions using Karnaugh Map.
4. implement the Boolean Functions using NAND and NOR gates.
5. analyze and design various combinational logic circuits.
6. understand the basic functions of flip-flops.
7. understand the importance of state diagram representation of sequential circuits.
8. analyze and design clocked sequential circuits.
This course makes significant contributions to the following program outcomes:
1. an ability to apply knowledge of mathematics, science, and engineering,
2. an ability to design and conduct experiments, as well as to analyze and interpret data,
3. an ability to design a system, component , or process to meet desired needs within realistic constraints
4. an ability to identify, formulate, and solve engineering problems,
5. an ability to use the techniques, skills, and modern engineering tools necessary for engineering practice.
- ASSIGNMENTS
ASSIGNMENTS
The homework assignments:
· The first page must be the title page. The title page must contain the name, surname and the number of the student. It should also contain the due date.
· Please also include a table of points for each problem.
· The solution must contain all the necessary steps.
· Remember that you must turn in the homework on the assigned days. Late submissions will not be accepted and graded.
Here is a sample title page. (You may download the .doc file and change the necessary information)
Important Note: You may discuss the homework problems with your friends for exchanging general ideas, but you may not copy from one another. You may also not give any parts of your homework to other students to look at. Any students violating these rules or committing any other acts of academic dishonesty WILL be turned over to the disciplinary committee for disciplinary action.
Homework II Cover Page File 52.9KB Word document Uploaded 27/10/17, 14:22
HOMEWORK I SOLUTIONS File 619.7KB PDF document Uploaded 13/11/17, 10:36
Design a combinational circuit that multiplies two binary numbers A and B. A is a 4 bit, and B is a 3-bit binary numbers. Use half-adders, full-adders and AND gates.
A3A2A1A0
x B2B1B0
__________
NOTE: You will submit your homework at the beginning of the class hour on Thursday, 14 December 2017.
- HW3 SOLUTION (PDF)
- LOGICLY FILE
- CHAPTER 1This topic
CHAPTER 1
Digital Systems and Binary Numbers
Digital Systems, Binary Numbers, Number-base Conversions, Octal and Hexadecimal Numbers, Complements, Signed Binary Numbers, Binary Codes, Binary Storage and Registers, Binary Logic
- CHAPTER 2
CHAPTER 2
Boolean Algebra and Logic Gates
Introduction, Basic Definitions, Axiomatic Definition of Boolean Algebra, Basic Theorems and Properties of Boolean Algebra, Boolean Functions, Canonical and Standard Forms, Other Logic Operations, Digital Logic Gates, Integrated Circuits
- CHAPTER 3
CHAPTER 3
Gate level Minimization
The Map Method, Two-variable map, Three-variable map, Four-Variable Map,Five-variable Map, Product of Sums Simplification,Don’t-care Conditions, NAND and NOR Implementation, Other Two-Level Implementations, Exclusive-OR Function
Solution of Class Problem by using Quine Mc-Cluskey Method
- CHAPTER 4
CHAPTER 4
Combinational Logic
Introduction, Combination Circuits, Analysis Procedure, Design Procedure, Binary Adder-Subtractor, Decimal Adder, Binary Multiplier, Magnitude Comparator, Decoders, Encoders, Multiplexers
- CHAPTER 5
CHAPTER 5
Synchronous Sequential Logic
Introduction, Sequential Circuits, Storage Element: Latches, Storage Element: Flip-Flops, Analysis of Clocked Sequential Circuits, State Reduction and Assignment, Design Procedure
- EXAMINATIONS
EXAMINATIONS
Past Exam Questions and Solutions
- Topic 10